搜索资源列表
digital_filter_src_n_doc
- design digital fiter. iir filter and fir filter. design and response function
mcu-89s52
- mcu89s52 数字电压表的设计 高精度 高阻抗-mcu89s52 the design of high-precision digital voltmeter high-impedance
szjhq
- 基于MATLAB的数字均衡器 设计与实现 -MATLAB-based Design and Implementation of Digital Equalizer
digital_voltmeter_and_hospital_call
- 简易的数字电压表的实现，和病房呼叫系统的实现，由出c51实现，其中本设计的病房呼叫系统在实际中得到应用 -Simple implementation of digital voltmeter, and the ward calling system implementation, from a c51 to achieve, in which the design of the wards call system has been applied in practice
MCU_Digital_Clock
- 单片机的数字钟设计,毕业设计,带Protel图,源代码用proteus软件仿真通过,附有毕设论文-Microcontroller digital clock design, graduate design with Protel map, the source code through the use proteus software simulation, with a Bi-based papers
QPSK_8PSKProject
- This project simulates the operation of wireless digital communications using Q-PSK and 8PSK modulator. The project consists of four steps: transmitter design, channel propagation effect, receiver design and finally measuring system performance.
Example3_3_4FilterFreqResponse
- 二维数字滤波器设计程序，用于频域滤波，非常好用！-2-D digital filter design
digitalwatch
- Describe: This VHDL digital clock, the use of digital control and FPGA design to achieve a number of counter clock, show hours, minutes ,seconds and alarm. The procedure depends on the metric system and consider six decimal counter preparation. The e
matlab-DSP
- 包括信号系统和系统响应，FFT谱分析，双线性法设计IIR数字滤波器，窗函数法设计FIR数字滤波器，四部分matlab仿真程序，以及必要的说明。-Including the signal system and the system response, FFT spectrum analysis, bilinear Design of IIR digital filters, window function method for the design FIR digital filters, fou
DigitadesignCPLD_VHDL
- Digital Design with CPLD and VHDL
High_Speed_FPGA
- This a PPT presentation named HSRA:High-Speed, Hierarchical Synchronous Reconfigurable Array (FPGA) prepared at the University of California at Berkeley. It gives a broad overview for beginners in the digital design with configurable logic. -This i
design
- 介绍了DDS(直接数字频率合成)基本原理,提出以DDS芯片AD9850为核心、利用单片 机控制辅以必要的外围电路,构成一个输出波形稳定、精度较高的信号发生器。该信号发生器主要能 产生幅度和频率分别可调的正弦波、方波与三角波。实验结果表明,硬件电路结构简单,输出信号频 率稳定率优于10 - 3 ,幅值误差低于5 。 关键词: DDS 集成芯片 AD9850 信号发生-Describes the DDS (direct digital frequency synthesis) bas
chx
- 以“低成本和高性能”为设计思想，借助虚拟仪器的概念和高速的数字信号处理算法将传统的函数发生器、示波器、数据记录仪、频率计、谱分析仪以及滤波器的设计和仿真等功能高度集成、统一平台方便使用。 -With " low cost and high performance" for design ideas, using the concept of virtual instruments and high-speed digital signal processing algorit
fm
- VHDL设计全数字FM接收机 资料大小：650KB 运行环境：Windows -VHDL design of all-digital FM receiver Data Size: 650KB operating environment: Windows
firgui
- fir digital design very good
DigitalDesignandModelingwithVHDLandSynthesis
- Digital Design and Modeling with VHDL and Synthesis
Digital
- 基于TI公司2812芯片的感应电机控制程序，比较完整，可用于实验室的平台设计-The induction motor control program based on DSP 2812 of TI, can be used in the design of the experiment plantform in laboratories.
digital-clock
- 该数字钟论文是我用了一周的时间，采用Verilog DHL语言设计， Quratuse8.1仿真通过的文章-This paper is a digital clock I used a week, Verilog by DHL language design, Quratuse8.1 simulation through the article
The_Final_Exp
- 嵌入式系统课程设计题目（2009年） 七段数码管数字钟（▲） 关键词：数字时钟 1、 硬件：JXARM9-2410教学实验箱，PC机。 2、 软件：PC机操作系统Windows（2000、XP）ADT IDE集成开发环境。 -Design of Embedded Systems Course Title (2009) seven-segment digital tube digital clock (▲) Keywords: digital clock 1, the hard
lvboqisheji
- 设计一个IIR数字低通滤波器， 逼近一组模拟滤波器的指标参数（通带截止频率Wp=2*pi*2000rad/s,阻带边界频率Ws=2*pi*3000rad/s,通带波纹 Rp=3db, 阻带衰减Rs=15db, 采样频率f=10000Hz）； 分别用脉冲响应不变法和双线性变换法实现设计，列出传递函数并描绘模拟和数字滤波器的幅频和相频响应曲线。用上述设计滤波器完成几组给定信号的滤波，证明滤波器的有效性和滤波范围限制.-Design a IIR digital low-pass filter, app